
`timescale 1ns / 1ns
module CameraConfigTest ; 

  wire   ioSda   ; 
  wire   oSclk   ; 
  reg    iRstN   ; 
  reg    iClk   ; 
  CameraConfig   DUT  ( 
      .ioSda (ioSda ) ,
      .oSclk (oSclk ) ,
      .iRstN (iRstN ) ,
      .iClk (iClk ) 
  ); 


// "Clock Pattern" : dutyCycle = 50
// Start Time = 0 ns, End Time = 1 us, Period = 20 ns
  initial
  begin
	  iClk  = 1'b0  ;
	  repeat(50) begin
		# 10	  iClk  = 1'b1  ;
		# 10	  iClk  = 1'b0  ;
	  end
  end


// "Constant Pattern"
// Start Time = 0 ns, End Time = 1 us, Period = 0 ns
  initial
  begin
	  iRstN  = 1'b1  ;
	 # 1000 ;
// dumped values till 1 ns
  end

  initial
	#1000 $stop;
endmodule
